ASIR: Application-Specific Instruction-Set Router for NoC-Based MPSoCs
Abstract
:1. Introduction
2. Related Work
2.1. Design of NoC-Based MPSoC
2.2. High-Level Synthesis
2.4. Programming and Task Map**
3. Hardware Architecture of ASIR
3.1. Processing Unit
1: | void processing_core(int* A, int* B){ |
2: | #pragma HLS INTERFACE axis port=A |
3: | #pragma HLS INTERFACE axis port=B |
4: | //Following code is application-specific |
5: | int threshold=110; |
6: | if (*A < threshold){ |
7: | *B=0; |
8: | }else{ |
9: | *B=1; |
10: | } |
11: | } |
3.2. Instruction and Data Flow through the Processing Unit
- Initially, the FSM is in the Release state. The header flit of a message is forwarded through the first multiplexer to the buffer in this state. The second multiplexer transmits the output of the buffer to the crossbar. The configuration of the processing core by setting the control signals is also done in this state.
- Afterwards, the instruction flit enters the buffer, which leads to a change from the Release state to the Reserve state. This state change requires that the instruction flit contains the corresponding address of the router; otherwise, the FSM remains in the Release state. The Reserve state sets the first and second multiplexer to the processing core. In addition, the counter increments at every incoming flit until it reaches the number of flits that is specified in the instruction flit. Furthermore, the instruction flit stored in the buffer is removed.
- The FSM changes from the Reserve state to the Idle state at the moment when the counter reaches the specified number of flits. The Idle state disables the first multiplexer so that no new flit can be forwarded to the processing core, as well as the buffer.
- The Release state is active again when the last flit of the processing unit has been transmitted. In Figure 5, the tail flit, which identifies the end of the message is transmitted through the buffer. However, further payload flits can be also transmitted.
4. Programming and Map** of ASIR-Based MPSoCs
4.1. Kahn Process Networks
4.2. KPN-Based Graphs for ASIR-Based MPSoCs
4.3. Map** of KPN-Based Graphs on an ASIR-Based MPSoC
- The path length to the MicroBlaze processor that executes the last mapped node must be greater than the length of R.
- The routers that are used in this path must have enough available buffers free for all nodes in R.
5. Evaluation
5.1. Image Processing Algorithm
5.2. Resource Utilization
Author Contributions
Funding
Conflicts of Interest
References
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Address | MicroBlaze | Router | Path Length | |||||
---|---|---|---|---|---|---|---|---|
x | y | N | E | S | W | L | ||
0 | 0 | v1 | v5 | - | - | - | - | 1 |
0 | 1 | v6 | - | - | - | - | - | 2 |
1 | 0 | v4 | - | - | v3 | - | - | 2 |
1 | 1 | v3 | - | - | - | - | - | 3 |
LUTs | FFs | BRAMs | DSPs | |
---|---|---|---|---|
Buffer | 3 | 34 | 0 | 0 |
PU (Threshold) | 109 | 146 | 0 | 0 |
PU (RGB2Gray) | 109 | 148 | 0 | 1 |
LUTs | FFs | BRAMs | DSPs | |
---|---|---|---|---|
Router | 481 | 245 | 0 | 0 |
Router with PU (Threshold) | 600 | 361 | 0 | 0 |
Router with PU (RGB2Gray) | 601 | 363 | 0 | 1 |
LUTs | FFs | BRAMs | DSPs | |
---|---|---|---|---|
2 × 2 MPSoC | 6916 (13%) | 5649 (5.3%) | 124 (88.6%) | 0 |
2 × 4 MPSoC | 14,806 (27%) | 10,973 (10.3%) | 128 (91,4%) | 0 |
ASIR-based MPSoC | 9568 (18%) | 9815 (9.2%) | 124 (88.6%) | 1 |
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Rettkowski, J.; Göhringer, D. ASIR: Application-Specific Instruction-Set Router for NoC-Based MPSoCs. Computers 2018, 7, 38. https://doi.org/10.3390/computers7030038
Rettkowski J, Göhringer D. ASIR: Application-Specific Instruction-Set Router for NoC-Based MPSoCs. Computers. 2018; 7(3):38. https://doi.org/10.3390/computers7030038
Chicago/Turabian StyleRettkowski, Jens, and Diana Göhringer. 2018. "ASIR: Application-Specific Instruction-Set Router for NoC-Based MPSoCs" Computers 7, no. 3: 38. https://doi.org/10.3390/computers7030038