100 Gbps Dynamic Extensible Protocol Parser Based on an FPGA
1
National Network New Media Engineering Research Center, Institute of Acoustics, Chinese Academy of Sciences, No. 21, North Fourth Ring Road, Haidian District, Bei**g 100190, China
2
School of Electronic, Electrical and Communication Engineering, University of Chinese Academy of Sciences, No. 19(A), Yuquan Road, Shi**gshan District, Bei**g 100049, China
*
Author to whom correspondence should be addressed.
Electronics 2022, 11(9), 1501; https://doi.org/10.3390/electronics11091501
Submission received: 31 March 2022
/
Revised: 4 May 2022
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Accepted: 5 May 2022
/
Published: 7 May 2022
(This article belongs to the Section Networks)
Abstract
:In order to facilitate the transition between networks and the integration of heterogeneous networks, the underlying link design of the current mainstream Information-Centric Networking (ICN) still considers the characteristics of the general network and extends the customized ICN protocol on this basis. This requires that the network transmission equipment can not only distinguish general network packets but also support the identification of ICN-specific protocols. However, traditional network protocol parsers are designed for specific network application scenarios, and it is difficult to flexibly expand new protocol parsing rules for different ICN network architectures. For this reason, we propose a general dynamic extensible protocol parser deployed on FPGA, which supports the real-time update of network protocol parsing rules by configuring extended protocol descriptors. At the same time, the multi-queue protocol management mechanism is adopted to realize the grou** management and rapid parsing of the extended protocol. The results demonstrate that the method can effectively support the protocol parsing of 100 Gbps high-speed network data packets and can dynamically update the protocol parsing rules under ultra-low latency. Compared with the current commercial programmable network equipment, this solution improves the protocol update efficiency by several orders of magnitude and better supports the online updating of network equipment.
1. Introduction
In recent years, with the explosive growth of bandwidth-intensive industries, such as video streaming and the industrial Internet of Things, efficient data distribution and acquisition have gradually become the main requirements of internet applications. The traditional TCP/IP network architecture is based on an end-to-end communication mechanism between hosts. Therefore, the network entity does not support multi-address and variable address operations, which makes it difficult to meet the current content-based internet application mode.
In contrast, Information-Centric Networking (ICN) [1] adopts the idea of information identification and address separation, weakens the concept of the host, and allows naming information at the network layer to improve the security and flexibility of information transmission. As a new type of network, in order to facilitate the transition between networks and the integration of heterogeneous networks, the current mainstream ICN network architecture at home and abroad also considers compatibility with TCP/IP network characteristics. For example, DONA [2] uses flat names to replace hierarchical URLs, uses top-level resolution services to decouple content and host addresses, and uses IP routing for data transmission.
NetInf [3] published and analyzed information through the assembly interconnection network and directly used the analysis node to request content, and the information return was still based on the underlying network transmission. SEANet [4] is a network architecture with on-site, flexible, and autonomous features. It adopts SeaDP, a transport layer protocol that expands and supports ID-to-ID on the basis of IPV6, for efficient data block transmission.
Therefore, these ICN network architectures are built on the basis of common network protocols. By extending the customized ICN protocol on the basis of the general Ethernet protocol or the IP-layer protocol, a transmission channel based on information identification is established.
As the core module for protocol parsing in most network transmission devices, the parser’s goal is to identify the protocol types in packet header fields and to allocate appropriate processing logic according to the protocol types, such as protocol-based packet filtering, more accurate routing and forwarding [5], etc. This article summarizes three key features of a high-performance parser in ICN network architecture: first, it can support efficient parsing of the general network protocols, which is the basis for integration with existing IP networks; second, it can identify customized ICN protocols to ensure that network equipment has better scalability; and third, packets can pass through the parser with deterministic low latency, which is the fundamental guarantee for the best performance of the system.
At present, the latency introduced by the pure software-designed parser is relatively large, and it is difficult to achieve zero packet loss in a high-speed network. However, the traditional ASIC-based hardware parser makes it difficult to flexibly expand the ICN protocol parsing rules due to the fixed chip performance. Even if a hardware platform that supports reconfiguration is used, it is often necessary to recompile the parsing logic to update the protocol parsing rules, which makes it difficult to update the protocol parsing rules in real-time.
The ICN is an important architecture of the future network that is mainly used in large-scale and high-concurrency network environments; therefore, it has high requirements in terms of the delay and throughput. In addition, with the continuous expansion of network services, ICN networks designed for different application scenarios need to support more network protocols. However, the current commercial network transmission equipment supports a limited number of protocols and cannot flexibly expand new protocol parsing rules according to the requirements of different ICN networks.
Therefore, in this paper, we propose a 100 Gbps dynamic extensible protocol parser (DEPP) based on FPGA. DEPP supports the real-time expansion of new protocol parsing rules based on common high-priority network protocols, thereby, facilitating flexible deployment in various ICN networks. In addition, the real-time nature of the protocol extension is beneficial to the online update of network equipment and ensures the normal operation of the network. The main contributions of our work are as follows:
- (1)
- We use an FPGA to implement packet parsing and protocol management. The data transmission channel of the parser adopts a width of 512 bits and a clock frequency of 200 MHz, which enables it to identify various packet protocols at a line rate of 100 Gbps.
- (2)
- We propose a dynamic extension mechanism for the protocols, which allows extending new protocol parsing rules in real-time at arbitrary locations in the existing parser tree by passing descriptors containing protocol information.
- (3)
- We also provide a multi-queue management mechanism for extended protocols, which supports group management of extended protocol parsing rules. Different from existing parsers designed with a hierarchical pipeline structure, this method can manage the update and execution of various types of extended protocol parsing rules under the same framework and support the storage of more protocol parsing rules.
- (4)
- The bus protocol conversion module is used for stream mode data conversion from an AXI4 bus to an Avalon bus. This module allows the parser to receive two bus protocol signals, making it more flexible to deploy on the mainstream FPGA platforms, such as Intel and ** that needs to be further retrieved is selected. For example, if the packet contains the IPV4 protocol, the queue group of (Ref_pro == IPV4) should be further retrieved to determine whether the packet contains the extended protocol over IPV4.The specific parsing process is as follows: According to the relative offset between the extended protocol and its reference protocol, we locate the position of the field to be identified in the packet header. Then, we extract the 32 bits matching field from this position and compare it with the protocol field and mask stored in the queue group in turn; after the matching is successful, we judge whether we need to parse the second-level extended protocol according to the next_en flag bit.The parsing process of the second-level extension protocol is the same as the above method. However, its Ref_pro is the address of the queue where the first-level extension protocol is located. After the parsing is completed, the queue index where the extended protocol is located is output, and the corresponding transmission channel is allocated for the data.
5. Evaluation and Results
According to the overall framework of DEPP proposed before, we deployed it on Intel Arrias 10, which is a programmable 100 Gbps FPGA board. The parser is designed with SystemVerilog coding and uses C language to encapsulate the access control interface in user space for delivering extended protocol descriptors and queue status detection. The IXIA high-speed network traffic generation tool is used to generate test data streams to evaluate the performance of DEPP in terms of protocol extension and parsing.The device connection is shown in Figure 7. The data packets generated by IXIA device are parsed by DEPP deployed on the FPGA and then distributed to different processing units of the R730 server for a statistic. Finally, we loop the packet back to the IXIA device.The most important feature of the scheme is its high flexibility in the protocol extension. Using the descriptor mechanism, new protocol resolution rules can be added in any location of packets in real-time without affecting the normal running of network devices. Here, we test the average latency consumed by DEPP and TCAM parsers when adding new protocol parsing rules, respectively, and the test results are shown in Figure 8.The delay mainly includes the time to deliver the descriptor from the host and the time to process the descriptor in the hardware. In DEPP, we adopt a pipeline processing mechanism so that the average update delay gradually decreases with the increase of the number of burst transmission rules and is stable within 300 ns. In contrast, the time required for a TCAM-based [25] parser to update each rule is about 3.3 ms, which is four orders of magnitude higher than DEPP.However, the current mainstream hardware reconfigurable parsers mainly rewrite the parsing logic to add new protocols and then reload them into the hardware through synthesis, wiring, and other operations. The overall time overhead is at least in minutes. Secondly, compared with the protocol management method based on TCAM, only the valid field of the protocol and its mask information can be stored in the TCAM, and the protocol positioning logic is not included; however, the descriptor can add protocol parsing rules of any length to any position of the data packet, which has higher flexibility.In order to further verify DEPP’s processing performance and packet throughput of the new protocol resolution rules, five protocol parsing rules as shown in Table 3 are added by extending the protocol descriptor. Pro0 to Pr03 are first-level extension protocols constructed based on high-priority general protocols, and Pro4 is a second-level extension protocol added on the basis of Pro3. Furthermore, we use the IXIA device for sending and receiving packet test.First, the fixed packet size is 1024 bytes, and 10 million packets with the above five protocols are randomly generated at a rate of 100 Gbps using IXIA equipment. The result is shown in Figure 9a, where the blue represents the number of different protocol packets sent by IXIA, and the orange represents the packets passing through the parser. It can be seen from the figure that the number of sending and receiving is the same, indicating that the parser can flexibly handle packets with different protocols. In Figure 9b, we fix the protocol type to Pro0, test the rate of packets of different sizes, and show the percentage of the actual received rate versus the theoretical value on the broken line. From the rate statistics results, except for a small amount of packet loss in the transmission and reception of line-rate small packets, stable packet reception of 100 Gbps can be achieved in other cases. This shows that the parser has high throughput characteristics.In Figure 10, we show the transmission delay of DEPP and the software parser designed with DPDK in a data forwarding system with fixed parsing rules. In order to show the test results better, the software parser was deployed on the Dell R740 server equipped with Mellanox ConnectX-5 NIC. The testing process is as follows: we randomly send data packets containing four-level protocol parsing rules, such as VLAN, IPV4, UDP, and Pro1, and forward them to the ixia device after passing through the parser.Here, we use a fixed four-level protocol parse tree for evaluation, although both can support customizing more complex protocol parsing rules. From the delay test results, it can be clearly seen that, even if the kernel protocol stack is bypassed and the DPDK development kit with high-performance data packet processing is adopted, the transmission delay of data packets is at least microseconds or even milliseconds. In contrast, the transmission delay designed with the DEPP scheme is much smaller. Even if a data packet with a length of 4096 bytes is transmitted, the average delay can be stabilized at about 1200 ns, which greatly improves the processing efficiency of network data.Table 4 shows the resource usage of DEPP deployed in Arria10 with different queue depths. The coverage of DEPP is small, leaving enough resource space for additional logic development. Compared with Openflow’s limited support for 44 protocols, DEPP supports more protocol extensions and can meet a wider range of network protocol extension requirements.6. Conclusions
This paper proposes an ICN dynamically extensible protocol parser based on the FPGA platform, which supports a flexible expansion of protocol parsing rules and high-speed network packet parsing. It has a wide range of application values in data centers, computer clusters, and other traffic-intensive environments. In this solution, we introduced the extended protocol descriptor and multi-queue protocol management mechanism to realize dynamic updates and the efficient parsing of the customized ICN protocol parsing rules, which improved the flexibility and stability of the ICN network. Furthermore, the parser can be flexibly deployed on a variety of FPGA platforms through bus protocol conversion.The experimental results show that DEPP supports adding new protocol parsing rules in real-time on the basis of the general protocol parsing tree and can, in a 100 Gbps high-speed network, accurately identify packet protocols. The high scalability of the parser enables it to be better deployed in various ICN network architectures and supports online updates of network devices, thereby, reducing the network downtime or network congestion caused by protocol updates and meeting future network requirements for high performance and flexibility.At present, DEPP can support the flexible expansion of new protocol parsing rules at the end of the protocol parsing tree; however, it cannot support inserting new protocols in the middle of the original parsing process or even at the root. This is also the focus of my future work.
Author Contributions
Conceptualization, K.W. and Z.G.; Investigation, K.W., M.S. (Mangu Song) and M.S. (Meng Sha); Methodology, K.W. and Z.G.; Project administration, Z.G.; Software, K.W.; Supervision, Z.G.; Validation, K.W.; Writing–original draft, K.W.; Writing–review & editing, Z.G., M.S. (Mangu Song) and M.S. (Meng Sha). All authors have read and agreed to the published version of the manuscript.
Funding
This work was funded by the Strategic Leadership Project of Chinese Academy of Sciences: SEANET Technology Standardization Research System Development (Project No. XDC02070100). This work was also funded by the IACAS Frontier Exploration Project (Project No. QYTS202006).
Data Availability Statement
All the necessary data are included in the article.
Conflicts of Interest
The authors declare no conflict of interest.
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Figure 1.
The abstract module of DEPP.
Figure 2.
Protocol extension diagram.
Figure 3.
Diagram of the queue.
Figure 4.
Bus protocol transformation diagram.
Figure 5.
Protocol update microstructure.
Figure 6.
The extended protocol detection process.
Figure 7.
Equipment connection diagram.
Figure 8.
The average update delay.
Figure 9.
Statistics of sending and receiving.
Figure 10.
Parsing latency variation.
Table 1.
Protocol parser performance overview.
| Type | Method | Flexibility | Delay | Throughput |
|---|---|---|---|---|
| software parser | Parser designed in software language on the host operating system | high | high | low |
| ASIC parser | Fixed-function commodity hardware parser | low | low | high |
| NetFPGA | A parser that supports the openflow protocol deployed in NetFPGA | low | low | high |
| RMT | A reconfigurable parser designed using P4 language | middle | low | high |
| HyperParser | A parser using butterfly network | middle | low | high |
| DEPP | dynamic extensible protocol parser based on FPGA | high | low | high |
Table 2.
Extended protocol descriptor.
| Field | Width (Bits) | Purpose |
|---|---|---|
| Ref_pro | 16 | Reference protocol |
| Epro_field | 16 | Valid fields of extension protocol |
| Epro_prefix | 5 | The field’s length |
| offset | 8 | The offset relative to the reference protocol |
| next_en | 1 | Next-level extended protocol enable signal |
| level | 16 | Level of the extension protocol |
Table 3.
Descriptor example.
| Ref_pro | Epro_field | Epro_prefix | Offset | Next_en | Level | |
|---|---|---|---|---|---|---|
| Pro0 | IPV4 | 0x00fe | 8 | 0x09 | 0 | 1 |
| Pro1 | UDP | 0x0087 | 8 | 0x0a | 0 | 1 |
| Pro2 | IPV6 | 0x00dd | 8 | 0x06 | 0 | 1 |
| Pro3 | VLAN | 0x8989 | 8 | 0x02 | 1 | 1 |
| Pro4 | Pro3 | 0x009b | 8 | 0x1f | 0 | 2 |
Table 4.
Resource utilization.
| Queue Depth | LUT (Total: 427,200) | Rigister (Total: 1,708,800) | RAM (Total: 55,562,240) | |||
|---|---|---|---|---|---|---|
| Used | Rate | Used | Rate | Used | Rate | |
| 32 | 5945 | 1.39% | 5334 | 3.12‰ | 22,656 | 4.07‱ |
| 64 | 10,375 | 2.43% | 7222 | 4.23‰ | 22,656 | 4.07‱ |
| 128 | 22,226 | 5.20% | 10,777 | 6.31‰ | 22,656 | 4.07‱ |
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Wang, K.; Guo, Z.; Song, M.; Sha, M. 100 Gbps Dynamic Extensible Protocol Parser Based on an FPGA. Electronics 2022, 11, 1501. https://doi.org/10.3390/electronics11091501
AMA Style
Wang K, Guo Z, Song M, Sha M. 100 Gbps Dynamic Extensible Protocol Parser Based on an FPGA. Electronics. 2022; 11(9):1501. https://doi.org/10.3390/electronics11091501
Chicago/Turabian StyleWang, Ke, Zhichuan Guo, Mangu Song, and Meng Sha. 2022. "100 Gbps Dynamic Extensible Protocol Parser Based on an FPGA" Electronics 11, no. 9: 1501. https://doi.org/10.3390/electronics11091501
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