A 6-Bit Ku Band Digital Step Attenuator with Low Phase Variation in 0.13-μm SiGe BiCMOS

Abstract

A 6-bit Ku band digital step attenuator with low phase variation is presented in this paper. The attenuator is designed with 0.13-μm SiGe BiCMOS process technology using triple well isolation N-Metal-Oxide-Semiconductor (TWNMOS) and through-silicon-via (TSV). TWNMOS is mainly used to improve the performance of switches and reduce the insertion loss (IL). TSV is utilized to provide approximately ideal global current ground plane with low impedance for the attenuator. In addition, substrate floating technique and new capacitance compensation technique are adopted in the attenuator to improve the linearity and decrease the phase variation. The measured results show that the attenuator IL is 6.99–9.33 dB; the maximum relative attenuation is 31.87–30.31 dB with 0.5-dB step (64 states), the root mean square (RMS) for the amplitude error is 0.58–0.36 dB and the phase error RMS is 2.06–3.46° in the 12–17 GHz frequency range. The total chip area is 1 × 0.9 mm².

1. Introduction

The attenuator is one of the key components of modern communications. It is widely used in the transmitter/receiver (T/R) module of phased array radar system [1,2], and its main function is to achieve amplitude control. Compared with the X-type attenuator [3] and variable gain amplifier (VGA) [4,5], the passive digital step attenuator has the advantages of low power consumption, high linearity, wide frequency band and low temperature drift. Therefore, the design of attenuator with high resolution, large attenuation, low IL and low phase variation has great value, and very broad application prospects.

A variety of passive attenuator circuits have been designed in [6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24]. There are three most-used topologies in the passive attenuators: Switched path attenuators [6,7,8,9], distributed attenuators [10,11] and switched T/Pi attenuators [12,13,14,15,16,17,18,19,20,21,22,23,24]. Switched path attenuators topology use single-pole-double-throw (SPDT) switches to control the signal between reference thru line path and the resistive attenuation network path. This topology exhibits low phase variation, but has high insertion loss and large chip area, so it is not suitable for multi-bit CMOS digital step attenuator. Transistors as varistors and the half/quarter-wavelength of the transmission lines (TLs) together constitute the distributed attenuators topology. Due to the relative attenuation signal paths across the transmission lines have no series switches, this topology has the advantage of low IL. Meanwhile, the use of the TLs greatly increases the chip area. Switched T/Pi attenuators topology is composed by the resistor attenuation network and series shunt single-pole-single-throw (SPST) switches. Its chip area is very compact and suitable for multi-bit integration.

In order to meet the design requirements of phased array system for attenuators with high resolution, large attenuation, low IL and low phase change, this paper proposed a 6-bit CMOS digital step attenuator using switched T/Pi topology. The switches are designed and optimized by TWNMOS and through-silicon-via (TSV), in order to improve the performance and reduce the IL of the switches. Moreover, the attenuator adopted substrate floating and new capacitance compensation technology, which improved linearity and reduced the phase variation.

2. Proposed Circuit Design and Analysis

The switch is one of the key building blocks in the digital step attenuator [25,26]. In this paper, the triple well isolation NMOS is adopted in the switch shown in Figure 1a. Figure 1b,c illustrate the simplified equivalent circuits for on-state and off-state of the switch. As shown in Figure 1, the on-resistance R_ch and parasitic resistance at source and drain terminals of NMOS switch will contribute to the insertion loss in the signal path. The parasitic capacitors C_GS, C_GD, C_SB and C_DB will contribute to the off-capacitance C_off of NMOS switch and act as a leak path from input to output at the off-state. A large resistor R_G (10 kΩ) is used to prevent the RF signal from leaking through the bias line. Body floating technique is used to improve power handling of the switch by reducing the signal loss through source/drain-to-body junctions. To implement this technique, a large resistor R_B (10 kΩ) is added to the body terminal of the switch to enhance the linearity and insertion loss performance. Meanwhile, TSV is utilized to provide approximately ideal global current ground plane with low impedance for the attenuator.

Inductive and capacitive correction structure digital step attenuator is adopted in [18] to achieve low phase variations. Although the inductance correction structure can achieve low IL, it occupies a large chip area. Capacitance correction structure has the advantages of lower phase variation and better agreement with simulation results in the broadband frequency range, but it has larger IL than inductance correction structure. In order to solve the contradiction between large IL and low phase variation of capacitance correction structure, especially large attenuation units, such as 8 dB and 16 dB attenuation cells. A new capacitance compensation technique is proposed in this paper. The topology of the proposed capacitance compensation correction network attenuation cell circuits in the digital step attenuator is shown in Figure 2.

In the proposed circuit structure, a parallel capacitor C_P is added to the shunt branch of the traditional T-type attenuator in Figure 2a. R_on is the on-resistance, and C_off is the off-capacitance of the transistor. When the switch M₁ is on, and M₂ is off, the attenuator works in the reference state. The signal passes through the series path, as shown in Figure 2b. When the switch M₁ is off, and M₂ is on, it works in the attenuation state. The signal flows from the shunt attenuation branch to the ground, as shown in Figure 2c. Parallel capacitor C_P is introduced as a phase correction device in the attenuation branch. Therefore, the correction network will affect the performance of the attenuation state. In order to facilitate the theoretical analysis, the TSV and body series parasitic inductance are neglected. The simplified equivalent circuit of the phase correction branch is as shown in Figure 2d, and the transmission phase of the network can be derived from the transmission (ABCD) matrix of the attenuation state; the equation of transmission phase θ can be deduced as follows (see Appendix A for detailed derivation):

$$\theta ={\tan }^{-1}\frac{-C_p{R}_p^2(Z_0+R_s)}{(R_p+R_{on})(2R_p+2R_{on}+Z_0+R_s)/\omega +2R_p^4{C}_p^2\omega +R_p^2{C}_p(Z_0+R_s)},$$

(1)

where ω is the operating angular frequency. Z₀ is the characteristic impedance. For simplicity, all parameters in the equation are treated as the constant except the operating angular frequency ω.

The theoretical mathematical analysis image of function θ can be drawn using MATLAB in Figure 3a. The slope of θ changes from negative to positive value at the broadband angular frequency range. When the slope is zero, there exists a critical frequency f (f = ω/2π), which can be used to correct the transmission phase error.

Figure 3b shows the practical simulation results in 0.13 μm SiGe BiCMOS process of the transmission phase of the phase correction branch in Figure 2d. The transmission phase varies with parallel C_p value (swept from 60 fF to 180 fF) at the broadband frequency range. Figure 3a,b possess a similar variation tendency, which verifies the theoretical analysis results in Equation (1).

Figure 4a shows the proposed T-type attenuator topology transmission phases of reference and attenuation states are simulated with various parallel capacitor C_p value. The phases of attenuation states have the same variation trend as those of the phase correction branch in Figure 3b.

It is obvious that the capacitance variation influences the attenuation state significantly, whereas, it has less effect on the reference state. By adjusting the capacitance C_p value, we can control the transmission phase of reference and attenuation states to intersect at different frequencies to produce zero phase difference. The low phase difference in a specific frequency band can be achieved by choosing the appropriate capacitance C_p value, as shown in Figure 4b.

Figure 5a shows the simulation attenuation results with traditional T-type and proposed C_p T-type topology in 4 dB attenuation cell. The simulation phase difference results with traditional T-type and proposed C_p T-type topology in 4 dB attenuation cell is illustrated in Figure 5b. With C_p compensation circuit structure, Flatness of the phase difference is better in a wide bandwidth range.

Meanwhile, in order to study the influence of TSV on phase difference, parasitic parameters of TSV with different sizes can be obtained by the electromagnetic field (EM) simulation.

Table 1. Parasitic inductance and resistance of TSV with different sizes.

Number of Row Vias.	Number of Column Vias	Parasitic Inductance (pH)	Parasitic Resistance (mΩ)
1	3	33	37
2	2	28	26
1	7	23	17
1	12	17	9
2	7	15	10
2	5	11	5
2	12	8	5
2	22	6	3

shows parasitic inductance and resistance of TSV with different sizes.

TSV is utilized to provide approximately ideal global current ground plane with low impedance for the attenuator. Take the proposed C_p T-type topology in 4 dB attenuation cell as an example, the TSV connected to the switch body terminal mainly provides on-chip grounding of the substrate, and its effect on the phase variation of the attenuator can be neglected. The TSV connected to capacitance compensation correction branch of the attenuation cell also provides on-chip grounding. The parallel capacitor C_p grounding terminal of the capacitance compensation correction branch in attenuation cell is not ideal, which results in an additional phase variation of the attenuator circuit. Although the effect of TSV on attenuator performance is small, it cannot be ignored. The simulation phase difference results with TSV size variation in proposed C_p T-type topology in 4 dB attenuation cell is illustrated in Figure 6. In microwave and millimeter wave bands, TSV will inevitably introduce parasitic inductance and resistance. The parasitic parameters are related to their size (i.e., the number of rows and columns vias). The larger the size, the smaller the parasitic inductance and resistance, but the bigger size will occupy a large area of the layout, so a compromise should be considered. After careful consideration, the TSV size of 2 × 5 was selected in this design.

The proposed capacitance compensation correction network and switch are also applicable to the Pi and bridge-T type attenuation cells. They have the same operation principle to realize low phase difference as the proposed T-type attenuator topology.

Traditional capacitance C_c and C_p compensation correction networks are widely used in the digital control step attenuator circuit [18,20,21], but there are large insertion losses, especially in large 8 and 16 dB attenuation units. In order to solve this problem, a parallel capacitor C_p is added to the attenuation shunt branch in 8 and 16 dB attenuation cells. Take 16 dB attenuation unit as an example: Figure 7a shows the simulation IL results with traditional C_c and proposed C_c + C_p compensation in 16 dB attenuation cell. The IL decreases obviously with the increase of frequency in the proposed C_c + C_p compensation structure. The simulated attenuation, phase difference results with traditional C_c and proposed C_c + C_p compensation in 16 dB attenuation cell is illustrated in Figure 7b. With C_c + C_p compensation circuit structure, the attenuation and phase difference change more smoothly in a wide frequency band.

Through the above theoretical and simulation analysis, in the proposed 6-bit digital control step attenuator circuit, 0.5 db, 1 db, 2 dB and 4 dB attenuation units adopt the proposed parallel capacitor C_p compensation method, which reduces the additional phase shift of attenuation. In the large attenuation unit (8 db, 16 db), we combine the traditional capacitance compensation method with the proposed parallel capacitance C_p compensation method, which reduces the problems of excessive insertion loss and large phase shift fluctuation range in the traditional capacitance compensation method.

The utilized attenuation cell topology in 6-bit CMOS digital control step attenuator is shown in Figure 8. 0.5 dB, 1 dB and 2 dB attenuation cells are configured with switched bridge-T type in Figure 8a. 4dB attenuation cell is configured with switched T-type in Figure 8b. The switched Pi-type topology in Figure 8c is suitable for large attenuation cells, such as 8 and 16 dB cells. The block diagram of the proposed 6-bit digital control step attenuator is shown in Figure 9.

The component values of each attenuator unit are summarized in

Table 2. Component values of each proposed attenuator unit.

Atten. (dB)	Topology	Rs (Ω)	Ro (Ω)	Rp (Ω)	Rc (Ω)	W1,3,5 (μm)	W2,4,6,7 (μm)	Cc (fF)	Cp (fF)
0.5	Bridge-T	5.92	40.9	368	0	40	15	0	17
1	Bridge-T	15.7	74.1	1293	0	90	20	0	17
2	Bridge-T	20.7	164.6	873	0	80	20	0	83
4	T-type	15.3	0	90.5	0	80	15	0	50.7
8	Pi-type	0	0	91.1	53.7	60	15	84.2	58.1
16	Pi-type	0	0	50.1	70.6	20	15	102.5	152.2

. The 6-bit CMOS digital control step attenuator circuit is optimized in terms of linearity, loading effect and power processing ability. Finally, the bit ordering 0.5-4-8-2-1-16 dB sequence is adopted in this paper. The proposed attenuator is controlled by the 6-bit digital signal control circuit array, V_c1, V_c2, V_c3, V_c4, V_c5, V_c6, which are used to control 0.5 dB, 1 dB, 2 dB, 4 dB, 8 dB, 16 dB attenuation modules, respectively. The layout of series/parallel resistors are the key components in the attenuator design; and the resistance values need to be carefully selected. In particular, small resistance values are realized by parallel connection of large resistance to reduce the influence of process variation effects. The power consumption of the attenuator is extremely low, which is contributed by the dynamic power consumption of inverters in each attenuation module.

The full chip electromagnetic (EM) simulation of the proposed 6-bit digital control step attenuator except resistors, capacitors and NMOS switch transistors components is realized in ADS Momentum in order to further ensure the performance. The transmission RF lines between the circuits of each attenuation cell are used to connect each module, which improves the matching performance and adjusts the transmission phase characteristics. Both input and output impedances of the proposed attenuator are matched to 50 Ω.

3. Measurement Results

The proposed 6-bit digital control step attenuator has been designed and fabricated in 0.13-μm SiGe BiCMOS technology. The die photograph of the proposed 6-bit digital control step attenuator is depicted in Figure 10. The total chip size is 1 × 0.9 mm². All the DC Pads are bond wired to a PCB for chip testing, and the chip is probed with Cascade’s 100 μm ground-signal-ground (GSG) probes at the input and output ports. The power consumption of the proposed attenuator is extremely low and negligible.

The input return loss (RL) is >13 dB in Figure 11a and the output return loss is >14.1 dB in Figure 11b at 10–18 GHz for the 64 states. Figure 12 shows the measured insertion loss (of the reference state) is 6.99–9.33 dB and IP_−1dB (of the reference state) is 13.6–16.2 dBm at 12–17 GHz. The maximum attenuation relative to that of the reference state is 31.87–30.31 dB with 0.5-dB step (64 states) at 12–17 GHz in Figure 13. The measured results show that the root mean square (RMS) for the amplitude error is 0.58–0.36 dB and the RMS phase error is 2.06–3.46° in the 12–17 GHz frequency range for the 64 states in Figure 14. The RMS for the amplitude error can be defined as:

$$A_{RMS}=\sqrt{\frac{1}{N}{\displaystyle \sum _{i=1}^N{\left(A_{m\_i}-A_{theo\_i}\right)}^2}}\left(dB\right),$$

(2)

where A_RMS is the attenuation RMS amplitude error, I is the attenuation state index, N is 64, A_{m_i} is the measured attenuation relative to the reference in a given state, and A_{theo_i} is the theoretical attenuation in a given state. The RMS phase error for the attenuation is calculated using the equation defined as follows:

$${\theta }_{RMS}=\sqrt{\frac{1}{M}{\displaystyle \sum _{i=1}^M{\left({\theta }_{m\_i}-{\theta }_{ref\_m}\right)}^2}}\left(deg\right),$$

(3)

where θ_RMS is the attenuation RMS phase error, i is the attenuation state index, M is 64, θ_{m_i} is the measured attenuation relative phase in a given state, and θ_{ref_m} is the measured attenuation relative phase in the reference state.

4. Comparison with Relevant Digital Control Step Attenuators

This work is compared with other recently published similar digital control step attenuators in

Table 3. Performance comparison of relevant digital control step attenuators.

Reference	[12] 2017	[13] 2017	[16] 2016	[17] 2018	[18] 2010	[21] 2018	This Work
Frequency (GHz)	19–21	14–18	6–12.5	20–24	DC–14	DC–20	12–17
Technology	0.18 μm CMOS	0.35 μm BiCMOS	0.25 μm BiCMOS	0.13 μm BiCMOS	0.18 μm CMOS	0.13 μm BiCMOS	0.13 μm BiCMOS
Number of Bits	6	6	7	6	6	6	6
Attenuation Rang (dB)	32	31.5	16.51	31.5	31.5	31.5	31.87–30.31
Attenuation Step (dB)	0.5	0.5	0.26	0.5	0.5	0.5	0.5
RL (dB)	>12	>10	>13	>9	>10	>12	>13
IL (dB)	<8	8±0.6	<12.7	20.9–21.95	<10	1.7–7.2	6.99–9.33
RMS Amplitude Error (dB)	N/A	<0.29	<0.26	<0.43	<0.5	<0.37	0.58–0.36
RMS Phase Error (°)	<3.8	<3.9	2.2–3.5	1.6–4.2	<4.2	<4	2.06–3.46
IP−1dB (dBm)	N/A	10	12.5	14	15	10	13.6–16.2
Die area (mm2)	0.451	0.271	0.291	0.772	0.51	0.982	0.92

^1. excluding pads ^2. including pads.

. The proposed 6-bit digital control step attenuator has better insertion loss compared with [16,17,18] and the higher IP_–1dB than [13,16,21]. Compared with [12,13,17], this design has wide frequency coverage. Even compared with all references in Table 3, the RMS phase error of this design has considerable competitive advantage. In this paper, the design of a 6-bit digital attenuator with low insertion loss and small RMS phase error in Ku-band (12–17 GHz) is realized by using substrate floating technology and the proposed capacitance compensation technology.

5. Conclusions

This paper has presented a 12–17 GHz 6-bit digital control step attenuator with low phase imbalance in 0.13-μm SiGe BiCMOS technology. In this design, a parallel capacitor C_p is added to the attenuation shunt branch of the traditional Pi, T and bridge-T type attenuation cells to form a phase correction network with the parallel resister. Furthermore, in order to study the influence of TSV on phase difference, parasitic parameters of TSV with different sizes can be obtained by an electromagnetic field (EM) simulation. After careful consideration, the TSV size of 2 × 5 was selected in this design. As far as the author knows, this is the first 6-bit digital attenuator designed with TSV. The influence of TSV on attenuator performance is also analyzed and verified. With the help of these techniques, the transmission phase error of the attenuation state can be corrected, thus, leading to a low phase imbalance. Meanwhile, substrate floating technology is adopted to reduce switches insertion loss and improve linearity. The proposed attenuator achieves the RMS phase error less than 3.46° and amplitude error less than 0.58 dB over 12–17 GHz. It has a maximum attenuation range of 31.87 dB with the approximate 0.5-dB step. In addition, good input/output return loss, high IP_–1dB, moderate chip area and wide bandwidth are obtained, which makes it suitable to use in Ku-band phased array systems.