A Parallel Connected Component Labeling Architecture for Heterogeneous Systems-on-Chip
Abstract
:1. Introduction
3. The Proposed Labeling Architecture
3.1. The Basic Rules
- If P(i,j) is surrounded by background pixels, it receives a new label Ln (with Ln = 1, …, NLAB − 1), and this event is recorded in TL by storing TL(Ln) = Ln and, at the same time, EM(Ln) = Ln.
- If the current neighborhood contains just one foreground pixel already labeled as Lx, then P(i,j) is provisionally labeled with TL(TL(Lx)), without updating TL and EM.
- If the neighbors are associated with two colliding labels Lu and Ll, P(i,j) is provisionally labeled with Lmin = TL(min(TL(Lu),TL(Ll))). Moreover, the newly identified equivalence is recorded in TL by storing TL(max(TL(Lu),TL(Ll))) = min(TL(Lu),TL(Ll)). At the same time, with Lmax = TL(max(TL(Lu),TL(Ll))), the equivalences EM(Lmax) and EM(Lmin) are resumed to update EM by storing both EM(EM(Lmax)) = EM(Lmin) and EM(Lu) = EM(Lmin).
3.2. Introducing the Parallelism
4. The Hardware Architecture of the Novel Parallel Labeling Approach
5. Results
Author Contributions
Funding
Conflicts of Interest
References
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P(i,j) | P(i,j + 1) | Ll | Lu1 | Lu2 | L(i,j) | L(i,j + 1) | Update TL | Update EM |
---|---|---|---|---|---|---|---|---|
0 | 1 | 0 | 0 | 0 | 0 | NewLab | TL(L(i,j + 1)) = NewLab | EM(L(i,j + 1)) = NewLab |
0 | 1 | 0 | 0 | >0 | 0 | TL(TL(Lu2)) | - | - |
0 | 1 | 0 | >0 | 0 | 0 | NewLab | TL(L(i,j + 1)) = NewLab | EM(L(i,j + 1)) = NewLab |
0 | 1 | 0 | >0 | >0 | 0 | TL(TL(Lu2)) | - | - |
0 | 1 | >0 | 0 | 0 | 0 | NewLab | TL(L(i,j + 1)) = NewLab | EM(L(i,j + 1)) = NewLab |
0 | 1 | >0 | 0 | >0 | 0 | TL(TL(Lu2)) | - | - |
0 | 1 | >0 | >0 | 0 | 0 | NewLab | TL(L(i,j + 1)) = NewLab | EM(L(i,j + 1)) = NewLab |
0 | 1 | >0 | >0 | >0 | 0 | TL(TL(Lu2)) | - | - |
1 | 0 | 0 | 0 | 0 | NewLab | 0 | TL(L(i,j)) = NewLab | EM(L(i,j)) = NewLab |
1 | 0 | 0 | 0 | >0 | NewLab | 0 | TL(L(i,j)) = NewLab | EM(L(i,j)) = NewLab |
1 | 0 | 0 | >0 | 0 | TL(TL(Lu1)) | 0 | - | - |
1 | 0 | 0 | >0 | >0 | TL(TL(Lu1)) | 0 | - | - |
1 | 0 | >0 | 0 | 0 | TL(TL(L1)) | 0 | - | - |
1 | 0 | >0 | 0 | >0 | TL(TL(L1)) | 0 | - | - |
1 | 0 | >0 | >0 | 0 | TL(Min(TL(Ll),TL(Lu1))) | 0 | TL(Max(TL(Ll),TL(Lu1)) = Min(TL(Ll), TL(Lu1)) | EM(EM(TL(Max(TL(Ll),TL(Lu1)))) = EM(Min(TL(Ll), TL(Lu1))); EM(Lu1) = EM(Min(TL(Ll), TL(Lu1))); |
1 | 0 | >0 | >0 | >0 | TL(Min(TL(Ll),TL(Lu1))) | 0 | TL(Max(TL(Ll),TL(Lu1)) = Min(TL(Ll), TL(Lu1)) | EM(EM(TL(Max(TL(Ll),TL(Lu1)))) = EM(Min(TL(Ll), TL(Lu1))); EM(Lu1) = EM(Min(TL(Ll), TL(Lu1))); |
1 | 1 | 0 | 0 | 0 | NewLab | NewLab | TL(L(i,j)) = NewLab | EM(L(i,j)) = NewLab |
1 | 1 | 0 | 0 | >0 | TL(TL(Lu2)) | TL(TL(Lu2)) | - | - |
1 | 1 | 0 | >0 | 0 | TL(TL(Lu1)) | TL(TL(Lu1)) | - | - |
1 | 1 | 0 | >0 | >0 | TL(TL(Lu1)) | TL(TL(Lu1)) | - | - |
1 | 1 | >0 | 0 | 0 | TL(TL(L1)) | TL(TL(L1)) | - | - |
1 | 1 | >0 | 0 | >0 | TL(Min(TL(Ll),TL(Lu2))) | TL(Min(TL(Ll),TL(Lu2))) | TL(Max(TL(Ll),TL(Lu2)) = Min(TL(Ll),TL(Lu2)) | EM(EM(TL(Max(TL(Ll),TL(Lu2)))) = EM(Min(TL(Ll), TL(Lu2))); EM(Lu2) = EM(Min(TL(Ll), TL(Lu2))); |
1 | 1 | >0 | >0 | 0 | TL(Min(TL(Ll),TL(Lu1))) | TL(Min(TL(Ll),TL(Lu1))) | TL(Max(TL(Ll),TL(Lu1)) = Min(TL(Ll),TL(Lu1)) | EM(EM(TL(Max(TL(Ll),TL(Lu1)))) = EM(Min(TL(Ll), TL(Lu1))); EM(Lu1) = EM(Min(TL(Ll), TL(Lu1))); |
1 | 1 | >0 | >0 | >0 | TL(Min(TL(Ll),TL(Lu1))) | TL(Min(TL(Ll),TL(Lu1))) | TL(Max(TL(Ll),TL(Lu1)) = Min(TL(Ll),TL(Lu1)) | EM(EM(TL(Max(TL(Ll),TL(Lu1)))) = EM(Min(TL(Ll), TL(Lu1))); EM(Lu1) = EM(Min(TL(Ll), TL(Lu1))); |
P(i,j) | P(i,j + 1) | Ll | Lcl | Lu1 | Lu2 | Lcr | L(i,j) | L(i,j + 1) | Update TL | Update EM |
---|---|---|---|---|---|---|---|---|---|---|
0 | 1 | x | 0 | x | 0 | 0 | 0 | NewLab | TL(L(i,j + 1)) = NewLab | EM(L(i,j + 1)) = NewLab |
x | 0 | x | >0 | 0 | 0 | TL(TL(Lu2)) | - | - | ||
0 | 1 | x | >0 | 0 | 0 | 0 | 0 | NewLab | TL(L(i,j + 1)) = NewLab | EM(L(i,j + 1)) = NewLab |
x | >0 | 0 | >0 | 0 | 0 | TL(TL(Lu2)) | - | - | ||
x | >0 | >0 | x | 0 | 0 | TL(TL(Lu1)) | - | - | ||
0 | 1 | x | x | 0 | 0 | >0 | 0 | TL(TL(Lcr)) | - | - |
x | x | x | >0 | >0 | 0 | TL(TL(Lu2)) | - | - | ||
x | x | >0 | 0 | >0 | 0 | TL(Min(TL(Lcr), TL(Lu1))) | TL(Max((TL(Lcr),TL(Lu1)) = Min(TL(Lcr), TL(Lu1)) | EM(EM(TL(Max((TL(Lcr),TL(Lu1)))) = EM(Min(TL(Lcr), TL(Lu1))); | ||
1 | 0 | 0 | 0 | 0 | x | 0 | NewLab | 0 | TL(L(i,j)) = NewLab | EM(L(i,j)) = NewLab |
x | 0 | >0 | x | 0 | TL(TL(Lu1)) | 0 | - | - | ||
>0 | 0 | 0 | x | 0 | TL(TL(L1)) | 0 | - | - | ||
1 | 0 | x | >0 | 0 | 0 | 0 | TL(TL(Lcl)) | 0 | - | - |
x | >0 | >0 | x | 0 | TL(TL(Lu1)) | 0 | - | - | ||
x | >0 | 0 | >0 | 0 | TL(Min(TL(Lcl),TL(Lu2))) | 0 | TL(Max(TL(Lcl),TL(Lu2)) = Min(TL(Lcl), TL(Lu2)) | EM(EM(TL(Max(TL(Lcl),TL(Lu2)))) = EM(Min(TL(Lcl), TL(Lu2))); | ||
1 | 0 | 0 | 0 | 0 | 0 | >0 | NewLab | 0 | TL(L(i,j)) = NewLab | EM(L(i,j)) = NewLab |
x | 0 | 0 | >0 | >0 | TL(TL(Lu2)) | 0 | - | - | ||
x | 0 | >0 | x | >0 | TL(TL(Lu1)) | 0 | - | - | ||
>0 | 0 | 0 | 0 | >0 | TL(TL(L1)) | 0 | - | - | ||
1 | 0 | x | >0 | x | 0 | >0 | TL(TL(Lcl)) | 0 | - | - |
x | >0 | 0 | >0 | >0 | TL(Min(TL(Lcl),TL(Lu2))) | 0 | TL(Max(TL(Lcl),TL(Lu2)) = Min(TL(Lcl), TL(Lu2)) | EM(EM(TL(Max(TL(Lcl),TL(Lu2)))) = EM(Min(TL(Lcl), TL(Lu2))); | ||
x | >0 | >0 | >0 | >0 | TL(TL(Lu1)) | 0 | - | - | ||
1 | 1 | 0 | 0 | 0 | 0 | 0 | NewLab | NewLab | TL(L(i,j)) = NewLab | EM(L(i,j)) = NewLab |
0 | 0 | x | >0 | 0 | TL(TL(Lu2)) | TL(TL(Lu2)) | - | - | ||
0 | 0 | >0 | 0 | 0 | TL(TL(Lu1)) | TL(TL(Lu1)) | - | - | ||
>0 | 0 | 0 | 0 | 0 | TL(TL(L1)) | TL(TL(L1)) | - | - | ||
>0 | 0 | 0 | >0 | 0 | TL(Min(TL(Ll), TL(Lu2))) | TL(Min(TL(Ll), TL(Lu2))) | TL(Max(TL(Ll),TL(Lu2)) = Min(TL(Ll), TL(Lu2)) | EM(EM(TL(Max(TL(Ll),TL(Lu2)))) = EM(Min(TL(Ll), TL(Lu2))); EM(Lu2) = EM(Min(TL(Ll), TL(Lu2))); | ||
>0 | 0 | >0 | x | 0 | TL(TL(L1)) | TL(TL(L1)) | - | - | ||
1 | 1 | x | >0 | 0 | 0 | 0 | TL(TL(Lcl)) | TL(TL(Lcl)) | - | - |
x | >0 | >0 | x | 0 | TL(TL(Lu1)) | TL(TL(Lu1)) | - | - | ||
x | >0 | 0 | >0 | 0 | TL(Min(TL(Lcl), TL(Lu2))) | TL(Min(TL(Lcl), TL(Lu2))) | TL(Max(TL(Lcl),TL(Lu2)) = Min(TL(Lcl), TL(Lu2)) | EM(EM(TL(Max(TL(Lcl),TL(Lu2)))) = EM(Min(TL(Lcl), TL(Lu2))); | ||
1 | 1 | 0 | 0 | 0 | x | >0 | TL(TL(Lcr)) | TL(TL(Lcr)) | - | - |
>0 | 0 | 0 | x | >0 | TL(Min(TL(Ll), TL(Lcr))) | TL(Min(TL(Ll), TL(Lcr))) | TL(Max(TL(Ll),TL(Lcr)) = Min(TL(Ll), TL(Lcr)) | EM(EM(TL(Max(TL(Ll),TL(Lcr)))) = EM(Min(TL(Ll), TL(Lcr))); EM(Lcr) = EM(Min(TL(Ll), TL(Lcr))); | ||
0 | 0 | x | >0 | >0 | TL(TL(Lcr)) | TL(TL(Lcr)) | - | - | ||
x | 0 | >0 | 0 | >0 | TL(Min(TL(Lu1),TL(Lcr))) | TL(Min(TL(Lu1),TL(Lcr))) | TL(Max(TL(Lu1),TL(Lcr)) = Min(TL(Lu1), TL(Lcr)) | EM(EM(TL(Max(TL(Lu1),TL(Lcr)))) = EM(Min(TL(Lu1), TL(Lcr))); | ||
>0 | 0 | >0 | >0 | >0 | TL(TL(Lcr)) | TL(TL(Lcr)) | - | - |
Ref n × m | Device | NLAB | MHz | ppcc | fps | LUTs | FFs | RAM (bits) | ResEFF | |||
---|---|---|---|---|---|---|---|---|---|---|---|---|
Logic | RAM | ShiftReg | Total | |||||||||
[14] 1,2 640 × 480 | XC4VLX160 | 4096 | 49.7 | 0.499 | 79.8 | - | - | - | 649 | 641 | 1142k + 560k | 1.2 |
[30] 704 × 480 | XC2VP100-6 | - | 140 | 1.387 | 574.4 | - | - | - | 3300 | - | 272k | - |
[22] 3 2k × 2k | EP1S25 | 1024 | 61.6 | 0.954 | 14.7 | - | - | - | 10k | 400k | 1.71 | |
[29] 1,4 1280 × 720 | 0.35 um | 4096 | 100 | 1.328 | 143.7 | - | - | - | 522 | 1434 | 9486k | 0.57 |
[19] 1 1k × 1k | XC6VLX240T | - | 185 | ≤0.5 | ≤88.21 | - | - | - | - | - | 108k | - |
[18] 640 × 480 | XC7Z020 | 64 | 142.8 | 0.954 | 464.8 | - | - | - | 17,861 | 4964 | 0 | 0.054 |
XC7Z045 | 128 | 225 | 0.954 | 732 | - | - | - | 76,622 | 17,396 | 0 | 0.025 | |
[15] 5 2k × 1.5k | XC7VX1140T | 7156 | 300 | ≤0.39 | ≤39 | - | - | - | 1329 | 1076 | 2592k | ≤1 |
New 640 × 480 | XC7Z020 | 64 | 91.3 | 1.906 | 594.2 | 271 | 80 | 130 | 481 | 566 | 0.375k | 3.93 |
XC7Z020 | 128 | 88.3 | 1.906 | 574.4 | 365 | 184 | 150 | 699 | 599 | 0.875k | 5.40 | |
XC7Z045 | 128 | 159.2 | 1.882 | 1036 | 382 | 184 | 150 | 716 | 599 | 0.875k | 5.21 | |
XC7Z020 | 256 | 79.3 | 1.904 | 515.4 | 470 | 432 | 170 | 1072 | 632 | 2k | 7 | |
XC7Z020 | 512 | 71.4 | 1.9 | 463.3 | 597 | 912 | 190 | 1699 | 665 | 4.5k | 8.73 | |
XC7Z020 | 1024 | 63.6 | 1.895 | 411.3 | 936 | 2080 | 210 | 3226 | 726 | 10k | 9.14 | |
New 2k × 2k | XC7Z020 | 64 | 97.3 | 1.908 | 46.4 | 288 | 80 | 416 | 784 | 1255 | 0.375k | 2.41 |
XC7Z020 | 128 | 80.5 | 1.904 | 38.4 | 364 | 184 | 480 | 1028 | 1288 | 0.875k | 3.67 | |
XC7Z020 | 256 | 77.1 | 1.908 | 36.8 | 463 | 432 | 544 | 1439 | 1321 | 2k | 5.24 | |
XC7Z020 | 512 | 72.6 | 1.906 | 34.6 | 593 | 912 | 608 | 2113 | 1354 | 4.5k | 7.08 | |
XC7Z020 | 1024 | 63.6 | 1.906 | 30.3 | 936 | 2080 | 672 | 3688 | 1415 | 10k | 8.07 | |
New 2k × 1.5k | XC7VX1140T | 8192 | 73.2 | 1.902 | 46.4 | 6518 | 21,504 | 864 | 28,886 | 2469 | 104k | 8.15 |
Reference N × m | Device | NLAB | Feature | MHz | fps | LUTs | FFs | RAM(bits) | |||
---|---|---|---|---|---|---|---|---|---|---|---|
Logic | RAM | ShiftReg | Total | ||||||||
[6] 640 × 480 | XC7Z020 | 256 | Area | 100 | 325.5 | 228 | 352 | 180 | 760 | 787 | 0 |
[7] 640 × 480 | XC2V3000 | 320 | BB | 97.07 | 316 | n.a. | n.a. | n.a. | 654 | 227 | 92k |
[8] 2k × 1k | XC6VLX240T | 64 | BB | 137.9 | 870.4 | n.a. | n.a. | n.a. | 42,792 | 17,376 | 2664k |
[9] 640 × 480 | XC2V6000 | 128 | Area | 40.63 | 105.8 | 1361 | 384 | 12 | 1757 | 600 | 72k |
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Perri, S.; Spagnolo, F.; Corsonello, P. A Parallel Connected Component Labeling Architecture for Heterogeneous Systems-on-Chip. Electronics 2020, 9, 292. https://doi.org/10.3390/electronics9020292
Perri S, Spagnolo F, Corsonello P. A Parallel Connected Component Labeling Architecture for Heterogeneous Systems-on-Chip. Electronics. 2020; 9(2):292. https://doi.org/10.3390/electronics9020292
Chicago/Turabian StylePerri, Stefania, Fanny Spagnolo, and Pasquale Corsonello. 2020. "A Parallel Connected Component Labeling Architecture for Heterogeneous Systems-on-Chip" Electronics 9, no. 2: 292. https://doi.org/10.3390/electronics9020292