An Adaptive Downsampling FPGA-Based TDC Implementation for Time Measurement Improvement
Abstract
:1. Introduction
2. FPGA-TDC Methodology
2.1. Tapped Delay-Line Architecture
2.1.1. TDL Cell
2.1.2. Ones-Counter
2.2. Placement of the TDL
2.3. Adaptive Downsampling Method
3. Results
3.1. Linearity Improvement
3.2. Effects of Nonidealities
3.3. Total Estimated Nonlinearity
4. Discussion
5. Conclusions
Author Contributions
Funding
Institutional Review Board Statement
Informed Consent Statement
Data Availability Statement
Conflicts of Interest
References
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Pat. | CCCC | CCCN | CCNC | CNCC | NCCC | CCNN |
DNL | 0.63 | 0.35 | 0.91 | 0.66 | 0.30 | 0.53 |
INL | 1.70 | 0.50 | 1.49 | 1.08 | 1.06 | 0.87 |
Pat. | CNCN | NCCN | CNNC | NCNC | NNCC | NNNC |
DNL | 0.12 | 0.46 | 0.95 | 0.49 | 0.19 | 0.19 |
INL | 0.52 | 0.62 | 0.86 | 0.83 | 0.51 | 0.47 |
Pat. | SSSS | SSSN | SSNS | SNSS | NSSS | SSNN |
DNL | 0.33 | 0.43 | 0.59 | 0.43 | 0.27 | 0.65 |
INL | 2.98 | 1.22 | 2.07 | 2.24 | 1.92 | 0.72 |
Pat. | SNSN | NSSN | SNNS | NSNS | NNSS | NNSN |
DNL | 0.19 | 0.39 | 0.58 | 0.26 | 0.51 | 0.19 |
INL | 0.90 | 0.56 | 1.36 | 0.98 | 1.13 | 0.47 |
Pat. | CSCC | SCCC | CSCN | SCCN | NSCN | SCNN |
DNL | 0.87 | 0.42 | 0.63 | 0.25 | 0.12 | 0.27 |
INL | 1.82 | 1.88 | 0.52 | 0.91 | 0.53 | 0.63 |
Pattern | Range | Range | ||
---|---|---|---|---|
CCCC | 0.78 | 0.86 | [4,−3] | [3,−3] |
CCCN | 0.69 | 0.85 | [3,−3] | [3,−2] |
CNCN | 0.45 | 0.52 | [2,−2] | [2,0] |
NNNC | 0.21 | 0.24 | [1,−1] | [0,−1] |
SSSS | 0.74 | 0.83 | [3,−3] | [3,−1] |
SSSN | 0.45 | 0.60 | [3,−3] | [0,−2] |
SNSN | 0.39 | 0.45 | [2,−1] | [1,−1] |
NNSN | 0.18 | 0.21 | [1,e1] | [0,−1] |
SCCC | 0.55 | 0.59 | [3,−4] | [3,−1] |
CSCN | 0.61 | 0.65 | [2,−3] | [2,−2] |
NSCN | 0.30 | 0.40 | [2,−2] | [0,−2] |
Pat. | CCCC | CCCN | CNCN | NNNC | SSSS | SSSN |
0.77 | 0.62 | 0.30 | 0.50 | 0.67 | 0.53 | |
1.57 | 0.65 | 0.45 | 0.69 | 2.94 | 1.39 | |
2.07 | 1.81 | 0.90 | 1.01 | 2.18 | 1.22 | |
4.03 | 1.76 | 1.12 | 1.28 | 6.10 | 3.27 | |
Pat. | SNSN | NNSN | SCCC | CSCN | NSCN | |
0.37 | 0.38 | 0.55 | 0.70 | 0.49 | ||
1.06 | 0.77 | 1.99 | 0.59 | 0.46 | ||
1.40 | 1.23 | 1.75 | 1.89 | 1.03 | ||
2.49 | 1.38 | 3.96 | 1.97 | 1.10 |
TDC | DNL | INL | FFs | LUTs | ||
---|---|---|---|---|---|---|
CCCC | 10 | 7.8 | 0.77 | 1.57 | 955 | 892 |
CCCN | 13.33 | 9.2 | 0.62 | 0.65 | 722 | 746 |
CNCN | 20 | 9.0 | 0.30 | 0.45 | 475 | 601 |
NNNC | 40 | 8.4 | 0.50 | 0.69 | 235 | 459 |
SSSS | 10 | 7.4 | 0.67 | 2.94 | 955 | 937 |
SSSN | 13.33 | 6.0 | 0.53 | 1.39 | 722 | 763 |
SNSN | 20 | 7.8 | 0.37 | 1.06 | 475 | 613 |
NNSN | 40 | 7.2 | 0.38 | 0.77 | 235 | 460 |
SCCC | 10 | 5.5 | 0.55 | 1.99 | 955 | 880 |
CSCN | 13.33 | 8.13 | 0.70 | 0.59 | 713 | 817 |
NSCN | 20 | 6.0 | 0.49 | 0.46 | 475 | 610 |
[20] | 10.1 | 9.82 | 0.52 | 1.08 | 1,641 | 577 |
[26] | 17.6 | 15 | [−1 0.8] | [−0.8 0.8] | NS | NS |
[30] | 10.54 | 3.39 | 0.29 | 0.63 | NS | NS |
[30] | 10.54 | 3.04 | 0.01 | 0.04 | 1,916 | 1,145 |
[18] | 25.57 | [0.69 1.46] | [−0.9 1.23] | [−0.44 2.96] | 415 | NS |
[33] | 8.5 | 0.36 | 0.91 | NS | NS | |
[21] | 8.7 | NS | [0 4.6] * | NS | NS | NS |
[25] | 10 | 10.3 | [−0.96 2.74] | NS | NS | 20,000 † |
[27] | 22.2 | 26.04 | 1.18 | 2.75 | 638 | 216 |
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Dikopoulos, E.; Birbas, M.; Birbas, A. An Adaptive Downsampling FPGA-Based TDC Implementation for Time Measurement Improvement. Chips 2022, 1, 175-190. https://doi.org/10.3390/chips1030012
Dikopoulos E, Birbas M, Birbas A. An Adaptive Downsampling FPGA-Based TDC Implementation for Time Measurement Improvement. Chips. 2022; 1(3):175-190. https://doi.org/10.3390/chips1030012
Chicago/Turabian StyleDikopoulos, Evangelos, Michael Birbas, and Alexios Birbas. 2022. "An Adaptive Downsampling FPGA-Based TDC Implementation for Time Measurement Improvement" Chips 1, no. 3: 175-190. https://doi.org/10.3390/chips1030012