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Volume 14
Issue 3
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J. Low Power Electron. Appl., Volume 14, Issue 3 (September 2024) – 2 articles

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12 pages, 1048 KiB  
Article
Spin–Orbit Coupling Free Nonlinear Spin Hall Effect in a Triangle-Unit Collinear Antiferromagnet with Magnetic Toroidal Dipole
by Satoru Hayami
J. Low Power Electron. Appl. 2024, 14(3), 35; https://doi.org/10.3390/jlpea14030035 - 3 Jul 2024
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Abstract
We investigate emergent conductive phenomena triggered by collinear antiferromagnetic orderings. We show that an up-down-zero spin configuration in a triangle cluster leads to linear and nonlinear spin conductivities even without the relativistic spin–orbit coupling; the linear spin conductivity is Drude-type, while the nonlinear [...] Read more.
We investigate emergent conductive phenomena triggered by collinear antiferromagnetic orderings. We show that an up-down-zero spin configuration in a triangle cluster leads to linear and nonlinear spin conductivities even without the relativistic spin–orbit coupling; the linear spin conductivity is Drude-type, while the nonlinear spin conductivity has Hall-type characterization. We demonstrate the emergence of both spin conductivities in a breathing kagome system consisting of a triangle cluster. The nonlinear spin conductivity becomes larger than the linear one when the Fermi level lies near the region where a small partial band gap opens. Our results indicate that collinear antiferromagnets with triangular geometry give rise to rich spin conductive phenomena. Full article
(This article belongs to the Special Issue Recent Advances in Spintronics)
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10 pages, 2548 KiB  
Article
Design and Analysis of Self-Tanked Stepwise Charging Circuit for Four-Phase Adiabatic Logic
by William Morell and **-Woo Choi
J. Low Power Electron. Appl. 2024, 14(3), 34; https://doi.org/10.3390/jlpea14030034 - 27 Jun 2024
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Abstract
Adiabatic logic has been proposed as a method for drastically reducing power consumption in specialized low-power circuits. They often require specialized clock drivers that also function as the main power supply, in contrast to standard CMOS logic, and these power clocks are often [...] Read more.
Adiabatic logic has been proposed as a method for drastically reducing power consumption in specialized low-power circuits. They often require specialized clock drivers that also function as the main power supply, in contrast to standard CMOS logic, and these power clocks are often a point of difficulty in the design process. A novel, stepwise charging driver circuit for four-phase adiabatic logic is proposed and validated through a simulation study. The proposed circuit consists of two identical driver circuits each driving two opposite adiabatic logic phases. Its performance relative to ideal step-charging and a standard CMOS across mismatched phase loads is analyzed, and new best practices are established. It is compared to a reference circuit consisting of one driver circuit for each phase along with a paired on-chip tank capacitor. The proposed driver uses opposite logic phases to act as the tank capacitor for each other in a “self-tanked” fashion. Each circuit was simulated in 15 nm FinFET across a variety of frequencies for an arbitrary logic operation. Both circuits showed comparable power consumption at all frequencies tested, yet the proposed driver uses fewer transistors and control signals and eliminates the explicit tank capacitors entirely, vastly reducing circuit area, complexity, and development time. Full article
(This article belongs to the Special Issue Ultra-Low-Power ICs for the Internet of Things Vol. 2)
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