FPGA-Based Reconfigurable Embedded Systems

A special issue of Electronics (ISSN 2079-9292). This special issue belongs to the section "Microelectronics".

Deadline for manuscript submissions: 31 July 2024 | Viewed by 560

Special Issue Editors


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Guest Editor
School of Computer and Information Technology, Bei**g Jiaotong University, Bei**g 100044, China
Interests: time-sensitive networking; hardware and software co-design; VLSI design

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Guest Editor
School of Software, Tsinghua University, Bei**g 100084, China.
Interests: computer architecture; industry data analytics

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Guest Editor
School of Computer, National University of Defense Technology, Changsha 410000, China
Interests: computer network architecture; deterministic network design; high-performance network hardware

Special Issue Information

Dear Colleagues,

Embedded systems are widely used across the entire world today, covering areas such as industrial controls, automotive electronics, medical electronics, consumer electronics, telecom/datacom, military/aerospace, etc. Reconfigurability is pushing embedded systems towards being more flexible, self-adaptive, and efficient. The customizable and programmable nature of FPGAs makes them an excellent alternative to ASICs as efficient hardware platforms for reconfigurable embedded systems. FPGAs provide opportunities for designers to quickly implement and evaluate different functions by reconfiguring the integrated computing logic and memory resources in the embedded systems.

However, FPGA-based reconfigurable embedded systems are very challenging because such systems, and especially the FPGAs, are typically constrained by limited computing, memory resources, bandwidth, power, and extreme environments. To tackle these problems, we need to refocus on the architecture, programming, implementation complexity, hardware and software co-design, etc., to determine the most efficient way to implement FPGA-based reconfigurable embedded systems. This Special Issue invites the submission of original contributions from both academic and industrial areas that focus on all topics related to FPGA-based reconfigurable embedded systems.

Topics

Topics of interests for this Special Issue include, but are not limited to, the following:

  • Novel reconfigurable architectures, including overlay architectures for embedded systems with FPGAs.
  • Resource-efficient/low-power/domain-specific design optimization for FPGA-based embedded systems.
  • Co-design of hardware and software for FPGA-accelerated embedded systems.
  • Abstractions, programming models, interfaces, and runtime management, including virtualization, for FPGA-based embedded systems.
  • New languages and design frameworks for spatial or heterogeneous applications for FPGAs.
  • System resilience/fault tolerance for embedded systems with FPGAs.
  • Self-adaptive/AI embedded systems with FPGAs.
  • Scheduling, management, and reconfiguration for real-time and/or networked embedded systems with FPGAs.
  • Emerging technologies with in-field reconfiguration abilities for embedded systems.
  • Industrial experience or case studies of FPGA-based reconfigurable embedded systems.

Dr. Zonghui Li
Dr. Yangdong Deng
Dr. Tao Li
Guest Editors

Manuscript Submission Information

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Keywords

  • embedded systems
  • FPGAs
  • reconfigurable architecture
  • hardware and software co-design
  • FPGA-accelerated embedded systems
  • real-time/networked embedded systems
  • AI/self-adaptive embedded systems

Published Papers (1 paper)

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Research

23 pages, 5565 KiB  
Article
Analysis and Construction of Hardware Accelerators for Calculating the Shortest Path in Real-Time Robot Route Planning
by Linton Thiago Costa Esteves, Wagner Luiz Alvez de Oliveira and Paulo César Machado de Abreu Farias
Electronics 2024, 13(11), 2167; https://doi.org/10.3390/electronics13112167 - 2 Jun 2024
Viewed by 189
Abstract
This study introduces an optimization approach for calculating the shortest path in mobile robot route planning. The proposed solution targets real-time processing requirements by offering a high-performance alternative. This is achieved by embedding in the dedicated hardware an architecture which emphasizes parallelism. Through [...] Read more.
This study introduces an optimization approach for calculating the shortest path in mobile robot route planning. The proposed solution targets real-time processing requirements by offering a high-performance alternative. This is achieved by embedding in the dedicated hardware an architecture which emphasizes parallelism. Through improvements in parallel exploration techniques, our solution aims to present not only a boost in performance but also a dynamic adaptation to graph changes, accommodating randomly occurring edge insertions or deletions as environmental conditions fluctuate. We present the developed architecture alongside its results. Our method efficiently updates obstacle matrices, resulting in a remarkable 120-fold improvement for 1024-node graphs. When utilizing a cost-effective device like the Cyclone IV E, it achieves approximately 12 times the performance of software applications. Full article
(This article belongs to the Special Issue FPGA-Based Reconfigurable Embedded Systems)
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